An Efficient Implementation and Analysis of Low Power High Performance Multipliers

Multipliers are optimized for low power which is of great interest in scientific and engineering field. There is large consumption of energy during the multiplication and addition process so an efficient implementation and analysis of different multipliers and adders are to be made to increase the performance. The multipliers used in multiplication process should involve low area, power and delay. Hence there is a need for optimization, as the performance of multiplier depends on the Multiplication process. The proposed work comprises the designing of 8-bit array multiplier and Baugh Wooley multiplier and analyzing the various parameters involved for optimizing the performance. The work has been done in a schematic editor using Tanner tool v7.00 in 20um CMOS technology. T-spice is used as simulator and W-editor is used for formal verification of the multiplier