A high-throughput maximum a posteriori probability detector

Areal density in magnetic storage systems has increased exponentially within the last few decades and this trend is predicted to continue. The increase in density adversely results in increased inter-symbol interference (ISI) and reduced signal to noise ratio (SNR). Sophisticated signal processing methods can be utilized to extract the data in such deteriorated signal environments. One method that has shown remarkable performance is iterative or turbo detection. Iterative detection requires soft outputs. Current detectors in magnetic devices use less computationally-intensive algorithms such as the Viterbi algorithm. Unfortunately, such algorithms generate hard outputs, which constrain the receiver to non-iterative processing. Algorithms such as soft-output Viterbi algorithm (SOVA) have been considered for iterative detection, but SOVA is a suboptimal algorithm in terms of bit error rate (BER) performance. In contrast, maximum a posteriori probability (MAP) detection based algorithms offer optimal BER performance. A MAP detector concatenated with a low-density parity-check (LDPC) code decoder is seen as a strong candidate for future high-density magnetic storage systems. However, due to high computational complexity, there has been a dearth of VLSI implementations for MAP detectors that target high-speed applications. This thesis work presents the design, implementation, and experimental verification of a MAP detector that can perform at very high throughputs. The implementation benefits from optimizations performed at several levels of system design. We chose to implement a forward-only algorithm that has several advantages over the traditional MAP algorithm. We propose a high throughput architecture for this detector. The high throughput is achieved by simplifying the throughput bottleneck at algorithm level with minimal effect on BER performance. More over we leverage techniques to increase throughput at the circuit level. Several test prototype chips were fabricated in 0.13μm CMOS and were experimentally verified. We present the hardware performance metrics of these chips in terms of power, throughput and area. The second part of this thesis concentrates on architectures for LDPC decoders. We propose a bit-node centric serial architecture for these codes. This architecture in generic stand-alone mode significantly reduces the memory requirement compared to other serial architectures. We propose a modification for this architecture targeted for LDPC decoders in iterative detectors. This further reduces the memory requirement and associated with less latency.