SystemVerilog for Verification

SystemVerilog for Verification

A Guide to Learning the Testbench Language Features

by Chris Spear

465 pages· 2008· ISBN 9780387765303
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About
Explains how to use the power of the SystemVerilog testbench constructs and methodology without requiring in-depth knowledge of Object Oriented Programming or Constrained Random Testing. This book covers the SystemVerilog verification constructs such as classes, program blocks, C interface, randomization, and functional coverage.

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