System Synthesis with VHDL

System Synthesis with VHDL

by Petru Eles

Browse books you can read free on Readfeed

No club is reading this yet — be the first to start one

Start a club free
About
Embedded systems are usually composed of several interacting components such as custom or application specific processors, ASICs, memory blocks, and the associated communication infrastructure. The development of tools to support the design of such systems requires a further step from high-level synthesis towards a higher abstraction level. The lack of design tools accepting a system-level specification of a complete system, which may include both hardware and software components, is one of the major bottlenecks in the design of embedded systems. Thus, more and more research efforts have been spent on issues related to system-level synthesis. This book addresses the two most active research areas of design automation today: high-level synthesis and system-level synthesis. In particular, a transformational approach to synthesis from VHDL specifications is described. System Synthesis with VHDL provides a coherent view of system synthesis which includes the high-level and the system-level synthesis tasks. VHDL is used as a specification language and several issues concerning the use of VHDL for high-level and system-level synthesis are discussed. These include aspects from the compilation of VHDL into an internal design representation to the synthesis of systems specified as interacting VHDL processes. The book emphasizes the use of a transformational approach to system synthesis. A Petri net based design representation is rigorously defined and used throughout the book as a basic vehicle for illustration of transformations and other design concepts. Iterative improvement heuristics, such as tabu search, simulated annealing and genetic algorithms, are discussed and illustrated as strategies which are used to guide the optimization process in a transformation-based design environment. Advanced topics, including hardware/software partitioning, test synthesis and low power synthesis are discussed from the perspective of a transformational approach to system synthesis. System Synthesis with VHDL can be used for advanced undergraduate or graduate courses in the area of design automation and, more specifically, of high-level and system-level synthesis. At the same time the book is intended for CAD developers and researchers as well as industrial designers of digital systems who are interested in new algorithms and techniques supporting modern design tools and methodologies.

Discuss System Synthesis with VHDL with other readers

Join or start a book club for System Synthesis with VHDL on Readfeed. Live chat, shared reading progress, and AI discussion questions — free to get started.

Frequently asked questions

How do I join a book club for System Synthesis with VHDL?

Sign up free on Readfeed, then browse public clubs or start your own club with System Synthesis with VHDL as the current read. Invite friends with a share link and discuss together with live chat and AI discussion questions.

Can I discuss System Synthesis with VHDL with other readers online?

Yes. Readfeed book clubs let you chat live, share progress, and join discussions about System Synthesis with VHDL with readers worldwide — whether your club is virtual, in-person, or hybrid.

Is Readfeed free?

Yes. Creating an account and joining book clubs is free. Sign up to find readers who love the same books and start discussing today.