Variation-aware processor architectures with agressive operating margins

Irregularities during the fabrication of a microprocessor and variations of voltage and temperature during its operation widen worst-case timing margins of the design--degrading performance significantly. These variations differ significantly in temporal and spatial scales. Process variations are static in nature, while voltage and temperature variations are highly sensitive to workload behavior, albeit at very different time scales. All sources of variation affect different parts of a microprocessor die in myriad ways with complex interactions and differ in their temporal and spatial characteristics. Microarchitectural techniques designed to mitigate parameter variations must clearly account for these differing characteristics. Traditionally, processors are designed for worst-case operating margins, losing substantial performance. This thesis explores an alternate approach to design for closer to nominal values, and providing mechanisms to tolerate unavoidable variation-induced errors. The initial focus of the thesis is to understand and deal with voltage variations and presents a low-overhead recovery mechanism coupled with an event-guided mechanism to prevent the recurrence of violations. Voltage variations represent only one dimension of the problem, so we extend our analysis to include the other two sources of variations. Doing so requires solutions that exploit the interactions as well as differences between these three sources of variations. Given that run-time variations like supply voltage droops and temperature fluctuations depend on the activity signature of the processor's workload, there are several opportunities to improve performance by dynamically adapting margins. This thesis also explores the power-performance efficiency gains that result from designing for typical conditions while dynamically tuning frequency and voltage to accommodate the run-time behavior of workloads. Such a design depends on a recovery mechanism that allows it to protect against margin violations during adaptation; we evaluate several such mechanisms, and we propose a local recovery scheme that exploits spatial variation among the units of the processor.