High Quality Delay Tests for Very Deep Submicron Designs

To meet the market demand, next generation of technology appears with increasing speed and performance driving manufacturing process to its limit. The, demand for low power consumption in battery operated devices, higher frequency and higher functional density has introduced new challenges to design and test engineers. Reducing power supply will lower the total power consumption but increases the circuit sensitivity to noise since the transistor threshold voltage is not scaling proportionally. Higher frequency and functional density will increase the power consumption producing more heat in the design and result in larger power supply noise. Integration of several cores for higher performance and throughput leads to longer interconnects thereby increasing coupling capacitance. As a result, performance verification has become one of the most challenging tasks for nanometer technology designs.