Electrostatic Modeling and Contact Resistance Engineering in 2D Semiconductor Devices

The ever-increasing demand for superior devices with a smaller footprint in electronics calls for research on novel materials as a potential replacement of or integration to the existing silicon-based technology. The emergence of two-dimensional semiconductors paved a promising path in this direction. Easy isolation of atomically thin and flat layers with dangling bond free surfaces enables these materials to not only form 2D vertical heterostructures with novel properties but also facilitates advanced transistor, diode, and tunnel-device design with characteristics such as unprecedented gate-control of the channel, extremely high mobility of charge carriers, high current density, and high on-off ratios. However, like any other technology at the early development phase, 2D semiconductor research also faces numerous challenges which are needed to be addressed. In this work, we address two such challenges in the field–modeling of vertical electrostatics in these complex novel devices which enables better understanding and prediction of their characteristics and overcoming the contact resistance issue in a promising 2D semiconductor, WSe2, which enables the advancement of these devices towards near-deal characteristics. To predict and analyze the electrical characteristics of 2D vertical heterostructures, we need to develop solid understanding of the potential landscape, charge distribution, and energy band diagrams in these devices. Conventional modeling approaches and simulation tools that have been used so far to simulate the transport characteristics obscure our intuition as the devices get more arbitrary and complex. Here, we developed a circuit equivalent model to simulate the vertical electrostatics in these novel and arbitrary heterostructures in a simple and intuitive manner. In our model, all the parameters of the energy band diagram are represented by equivalent circuit elements involving capacitors and voltage sources. We also provide an elegant approach to solve these circuits by using Gauss law in electrostatics and charge-neutrality conditions in quasi-equilibrium. With a computationally efficient algorithm developed to solve these structures, we further built an opensource tool 2dmatstack on nanohub.org that enables researchers to predict and analyze the characteristics of novel heterostructures to maximize research output. In the next section, we focus on a major bottleneck in realizing these vertical devices experimentally. Fermi-level pinning and process-induced surface damage cause large Schottky barriers between metal contacts and these ultrathin 2D semiconducting layers resulting in large contact resistance and poor, non-ideal device performance. The solution to this problem is much more developed in the most widely studied n-type candidate, MoS2, compared to the common the p-type candidate, WSe2. In this work, we develop a UV-ozone-based oxidation technique that transforms the top layer of WSe2 into a nonstoichiometric oxide, TOS, that degenerately dopes the layers underneath p-type. This high hole-doping decreases the Schottky barrier width at the contacts and has resulted in the lowest p-type contact resistance to ultrathin WSe2 reported thus far. We show that this doping is stable in the ambient, remains active at low temperatures, repeatable, robust, and area selective for contact-doping without altering the channel properties. The high-performance ohmic contacts we demonstrate not only sets us in the path to realize near-ideal channel-dominated devices but also is pivotal to understand these devices better by eliminating the effect of contacts from the gate-controlled channel characteristics.