Stuart Sutherland

• RTL modeling with SystemVerilog for simulation and synthesis using SystemVerilog for ASIC and FPGA design
• SystemVerilog for Design Second Edition: A Guide to Using SystemVerilog for Hardware Design and Modeling
• Breakdown
• Irracionalidad
• Irracionalidad
• Irrasyonel
• SystemVerilog For Design
• SystemVerilog for design
• SystemVerilog for Design Second Edition
• SystemVerilog ni yoru LSI sekkei
• The Verilog PLI Handbook
• Verilog - 2001